A. Field of the Invention
The present invention relates to electronic design, and more particularly to analysis of signal timing requirements in complex electronic systems.
B. Description of the Prior Art
Digital processing systems typically consist of a combinational logic network and bistable latch elements. The combinational logic network contains a large number of logic components that perform decision-making functions, while the latches serve as memory elements to temporarily store input, intermediate and output data, as well as control information. A clocking system mediates communication among the system components and state changes in the individual elements; usually, the state of the system changes at the occurrence of each clock pulse.
Components and groups of components have timing requirements that derive from specific operational features. Some requirements arise from hardware limitations; for example, a component may require establishment of a stable input signal for a certain minimum time interval before a stable output signal from that component can be achieved. Other requirements arise from system features such as bus characteristics, interface protocols or cycle times. Given the large number of interrelated timing requirements likely to be encountered in the design of even modest digital systems, methods of identifying and resolving timing conflicts are critical.
Two such methods are described in copending application Ser. No. 162,624 (commonly owned with the present application and hereby incorporated by reference), which describes identification of an optimized, reduced set of consistent timing requirements that deviates minimally from the set originally proposed by the user; and copending application Ser. No. 205,811 (commonly owned with the present application and hereby incorporated by reference), which describes prioritization of timing requirements. See also Sherman, Algorithms for Timing Requirement Analysis and Generation, Proc. of 25th ACM/IEEE Design Automation Conf. at 724 (1988).
One difficulty attending the use of such methods is presentation of th timing requirements of the various elements in a consistent format. Numerous ways of describing timing information currently exist, and engineers often find it difficult and tedious to accurately express this information in the manner most convenient for the timing resolution method. Ambiguities and errors are often introduced. Indeed, engineers collaborating on a project may have trouble communicating among themselves about timing-constraint issues. However, if such issues remain unaddressed until software simulation or construction of a prototype, expensive late-stage redesign work may become necessary.
A second issue relating to timing-constraint nomenclature involves computer-implemented design-assistance packages. These programs generally require not only a consistent terminology for specification information, but one that is also amenable to straightforward computer analysis. Ideally, information should be provided in a form that is terse and easily interpreted.
C. Objects of the Invention
Accordingly, it is an object of the present invention to provide a method of reducing an unstructured specification description to a consistent format.
It is another object of the invention to enable design engineers to enter specification information in a natural-language format.
It is a further object of the invention to provide symbolic specification descriptions that are easily interpreted by a computer.
It is yet another object of the invention to produce specification descriptions that are as free from ambiguity as the entered information permits.
D. Definitions
As used herein, the following terms have the meanings indicated opposite and with reference to FIG. 1:
State--Represents the condition of a node in an electrical system. PA1 Non-Transition State--In the timing diagram depicted in FIG. 1, non-transition states are designated by reference numerals 20, 22, 24, 26 and 28. A non-transition state can be logic level zero (states 20, 24 and 26), logic level 1 (states 22, 28), stable or high impedance. PA1 Transition State--Represents the boundary between sequential non-transition states in a signal. In FIG. 1, transition states are designated by reference numerals 30, 32 and 34. A transition state can be rise (zero-to-one transition states 30 and 34), fall (one-to-zero transition states 32), rise-fall or change. "Rise-fall" denotes an indeterminate transition state between two non-transition states and can include zero-to-one, one-to-zero and no-change. "Change" is similar to rise-fall but can also include transition to a high impedance state. PA1 Transition--Represents a boundary between states. Transitions are denoted collectively in FIG. 1 by reference numeral 38. PA1 Signal--Denotes a named sequence of states, e.g., signals A and B in FIG. 1. PA1 Timestamp--Denotes an absolute time value signifying when a transition will occur. Timestamps are denoted as t.sub.1 through t.sub.6 in FIG. 1. PA1 Pattern--Denotes a set of signals with timestamps. PA1 Dependence--Denotes a minimum or maximum time between transitions on the same or different specified signals (i.e., a timing constraint), and the importance of the constraint. For example, it may be necessary for the interval between t.sub.4 and t.sub.5 to assume or exceed a minimum critical value to permit reliable capture of signal data. PA1 Specification--Describes timing relationships among signals with less specificity than that found in a dependence. PA1 Dependence Connection--Establishes the transitions on a pattern or patterns to which a particular dependence relates.